Meta MTIA Architecture Revealed: 72x MTIA 400 Scale-Up and AEC Cable Design
jwt0625 · x · 2026-08-13
The author shares hardware architecture details of the Meta MTIA chip cluster, showcasing a scale-up system featuring 72x MTIA 400. This setup offers better topological symmetry than NVIDIA's NVL72 and utilizes AECs (Active Electrical Cables) for scale-out connections to switches.
Referencing an ISCA 2026 paper on MTIA 300 (Meta's first training chip with built-in NICs and collective offloading engines), the author discusses its specs based on 112G Serdes and 96 lanes. They question why the scale-up domain size is limited to 16, speculating it fits physical rack constraints, and critique traditional rack-style deployments.
Related event: Details of Meta's Custom AI Chip MTIA Architecture Revealed(2 posts)→
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