Meta MTIA 300 Architecture: Why Only 16 Scale-Up Domain With 96 SerDes Lanes?
jwt0625 · x · 2026-08-13
Raises questions and reflections regarding the hardware architecture design of Meta's latest custom AI chip, MTIA 300.
- Bandwidth Specs: The chip is equipped with 96 lanes of 112G SerDes, offering massive interconnect bandwidth potential.
- Scale-Up Bottleneck: Despite the high interconnect capacity, the scale-up domain size is limited to 16. The author speculates this is because only an 8+8 node configuration fits inside a single rack.
- Architecture Critique: The author expresses growing dislike for traditional rack-style arrangements, proposing alternative form factors like a "compute cylinder with a network core."
Related event: Details of Meta's Custom AI Chip MTIA Architecture Revealed(2 posts)→
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