vLLM Achieves Bitwise Train/Inference Parity for Gated DeltaNet

AccBalanced · x · 2026-08-07

The vLLM project announced that bitwise train/inference parity has been successfully achieved for linear attention when combining TorchTitan RL with vLLM.

Technical details reveal that Gated DeltaNet's recurrent kernel is batch-invariant: it relies solely on the sequence's own state and fixed order, without cross-sequence reductions. Experiments confirmed that the logprob diff is exactly 0, and existing prefix caching mechanisms work as-is without requiring modifications.

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