HBM Expansion Throttled by Packaging Bottlenecks
tengyanAI · x · 2026-07-19
- This post discusses the physical bottlenecks in HBM memory expansion: even if customers diversify from SK hynix to Samsung and Micron, it merely spreads the same substrate constraint across more buyers without genuinely alleviating the pressure.
- The post also notes that ISC test sockets are a critical chokepoint in HBM stacked DRAM certification; every additional wafer start at the three foundries consumes more sockets.
- Because the substrate capacity expansion cycle takes roughly 24 个月, the supply curve is highly inelastic. Thus, while the HBM premium has dropped from its peak, it hasn't completely "collapsed."
More from Infra
- SF Compute founder: buying compute is 'an absolutely awful experience' right now — IgorCarron · 2026-09-11
- SmolVM open-sources persistent computer infrastructure for agents that outlive chat sessions — aniketmaurya · 2026-09-11
- PyTorch Day Korea 2026 launches first offline conf, CFP closes Sept 13 — PyTorch · 2026-09-11
- Local LLM server dilemma: 4x CMP-170HX (price up 53% in 20 days) vs Mac Studio M5 Ultra — rumboll · 2026-09-11
- llama.cpp lands Flash Attention tuning for RDNA4, big prefill gains on AMD — pmttyji · 2026-09-11
- Your p99 latency benchmark may be lying: a deep dive into coordinated omission — Franc0Fernand0 · 2026-09-11