Moore Threads Post-Trains Qwen3.6 on Domestic Chips
teortaxesTex · x · 2026-07-10
The post states that Moore Threads used its in-house MTT S5000 chips to post-train Qwen3.6-27B. The model performs well in kernel engineering scenarios, with details mentioning the use of RL training methods.
More importantly, they tested the model on a MUSA-ported version of KernelBench, highlighting that the core focus of this news is the support for model post-training and engineering optimization provided by domestic computing power and software stacks.
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