Analyzing SMIC's DUV Process Defect Density
teortaxesTex · x · 2026-07-08
A post discusses the defect density of later-stage DUV lithography processes. The author notes that TSMC claimed a defect density of 0.09 in 2019. Drawing on SMIC's 6-year experience manufacturing Kirin chips with this process, the author conservatively uses a value of 0.15 in their calculations.
Related event: Analysis of Huawei Ascend Capacity and SMIC DUV Process(4 posts)→
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